60 nm Self-Aligned-Gate InGaAs HEMTs采用Mo金屬 - 副本

2023年12月13日發(fā)(作者：攤的四字詞語)

-

60 nm Self-Aligned-Gate InGaAs HEMTs

with Record High-Frequency Characteristics

Tae-Woo Kim, Dae-Hyun Kim and Jesús A. del Alamo

Massachutts Institute of Technology (MIT), Cambridge, MA 02139, U.S.A, E-mail: twkim78@

Abstract

We have developed a new lf-aligned gate technology for

InGaAs High Electron Mobility Transistors with non-alloyed

Mo-bad ohmic contacts and a very low parasitic capacitance

gate design. The new process delivers a contact resistance of 7

Ohm-μm and a source resistance of 147 Ohm-μm. The non-alloyed Mo-bad ohmic contacts show excellent thermal

stability up to 600 °C. Using this technology, we have

demonstrated a 60 nm gate length lf-aligned InGaAs HEMT

with gm = 2.1 mS/μm at VDS = 0.5 V, and fT = 580 GHz and

fmax = 675 GHz at VDS = 0.6 V. The are all record or near

record values for this gate length.

Introduction

Reducing source and drain parasitic resistance is esntial to

boosting the frequency respon of III-V High Electron

Mobility Transistors (HEMTs) [1-2]. A key to accomplishing

this is to shrink the source-gate contact paration, LGS. State-of-the-art III-V HEMTs typically feature LGS

values

in the

range of 0.5 to 1 μm which result in source resistance (Rs) in

InGaAs HEMTs of around 200 ohm-μm. The lowest source

resistance in InGaAs HEMTs has been reported by Matsuzaki

[3] as Rs = 100 Ohm-μm in non-lf-aligned devices with a

gate-source paration, LGS

= 100 nm. To improve beyond this,

a lf-aligned gate design is esntial.

Several lf-alignment schemes for InGaAs HEMTs have

been demonstrated in the literature [4-5]. In one approach, after

T-shape gate formation, ohmic metal is deposited using the

gate as a mask. This results in LGS of about half the gate head

size [4]. In a parate approach demonstrated by our group, W

was ud as non-alloyed ohmic contacts with the gate nested

inside an opening in a lf aligned way. Through this

technology 90 nm gate length InGaAs HEMTs were

demonstrated with LGS = 60 nm [5]. This technology featured a

simple lift-off gate with high parasitic capacitance. As a result,

the frequency respon of the fabricated transistors was

unremarkable.

In this work, we demonstrate a new lf-aligned gate

technology with non-alloyed Mo-bad ohmic contacts and a

very low parasitic capacitance gate design. The new process

delivers very low values of contact resistance and source

resistance and record high-frequency characteristics. The

propod device architecture allows for the incorporation of a

high-K gate dielectric in the gate stack to achieve MOS type

devices.

Process Technology

Fig. 1 shows a simplified process quence on a HEMT

heterostructure. Device fabrication starts with blank 20 nm Mo

e-beam evaporation after removal of the native oxide in an HCl

bad solution. This Mo layer rves as source and drain non-alloyed ohmic contact. The process follows with mesa

isolation, Ti/Mo ohmic pad, SiO2 sacrificial layer deposition

and Ti/Au contact pad formation.

Fig. 1

Process flow for SAG structure: a) double exposure and

double development e-beam process, b) CF4/H2/Ar bad plasma

etching to create opening in SiO2, c) CF4/O2 plasma to isotropically

etch Mo, and d) two-step gate recess process using Citric acid and

Ar plasma to expo barrier.

The first step in T-shape gate formation is a double-exposure

double-development gate resist process (Fig. 1a). This is

followed by etching of an opening in the SiO2 by anisotropic

CF4/H2/Ar bad plasma (Fig. 1b). We then carry out isotropic

etching of the Mo layer by CF4/O2 plasma (Fig. 1c) to place the

edge of the Mo contacts at a controlled distance away from the

edges of the gate (t by the edge of the SiO2 sacrificial layer).

Following this, we perform a two-step gate recess process

which consists of cap removal by a citric acid bad solution

followed by Ar bad plasma for the InP etch stop (Fig. 1d).

This results in a slight undercut of the Mo contact layer. We

then evaporate and lift off a Pt/Ti/Pt/Au gate stack followed by

a thermal step to drive the Pt into the InAlAs barrier and

achieve an effective barrier thickness of tins = 5 nm.

Devices with Lg in the range of 50 to 150 nm were

fabricated. Fig. 2 shows a schematic cross ction of the final

device. Fig. 3 shows STEM images of a fabricated Lg = 60 nm

device. The gate to source contact paration (LGS) and side-recess-length (Lside) were 100 nm and 200 nm, respectively.

978-1-4244-7419-6/10/$26.00 ?2010 IEEE30.7.1IEDM10-696better results than a Mo lift-off process due to the abnce of

residual photoresist at the metal-miconductor interface. Our

Mo contact technology is also thermally stable up to 600C.

Fig. 5 shows output characteristics of a typical Mo-bad

SAG HEMT with Lg

= 50 nm. The device exhibits excellent

saturating characteristics with low RON and a high current of

0.68 mA/μm at VDS = 0.5 and VGS-VT = 0.33 V (2/3 of VDS).

Fig. 6 shows typical current and transconductance

characteristics vs. VGS at VDS = 0.5 V. This device exhibits

over 2.2 mS/μm of maximum transconductance, a record value

for Lg = 50 nm HEMTs at VDS = 0.5 V. This result aris from

the reduced source resistance of the SAG structure.

Fig. 7 shows subthreshold characteristics for VDS = 50 mV

and 0.5 V. The subthreshold swing S = 120 mV/dec and DIBL

= 160 mV/V that we obtain are not as good as earlier

demonstrations from our group. This is the conquence of

slightly higher gate leakage current. An optimized

heterostructure and Pt sinking process should correct this.

3000

Rc=30 Ohm-μm

2500with Mo lift-off process

2000

Rc= 7 Ohm-μm with

blanket Mo deposition

1500

1000Rc= 60 Ohm-μm

with W-bad Ohmic

500

005101520

Lgap

[μm]

Fig. 4 TLM measurements for three different contact schemes.

The gap length in each contact was measured by SEM.

1.0VGS = 0.5 V

0.8

0.4 V

0.6DC and Microwave Characteristics

0.3 V

Fig. 4 shows resistance measurements in TLM structures.

We compare our approach using Mo blanket deposition and

0.4 0.2 Vdry etching with a scheme bad on standard Mo evaporation

plus lift-off. Also, as reference, we add earlier lf-aligned W-

0.2 0.1 Vbad ohmic results [5]. The new Mo-bad approach yields an

0 VRc of 7 Ohm-μm. This is nearly an order of magnitude

improvement over previous lf-aligned ohmic-contact

0.00.00.10.20.30.40.50.6

technology [5] and a record value among non-alloyed ohmic

VDS [V]

contacts to InGaAs FETs. Also, blanket Mo deposition yields

Fig. 5 Output characteristics of Mo-bad SAG HEMT with Lg =

50 nm.

ID

[mA/μm]

Fig. 2 Final cross ction of Mo-bad SAG HEMT.

Fig. 3 Cross-ction STEM images of Mo-bad SAG HEMT with

L = 60 nm with 100 nm gate-source contact paration and

gLside=200 nm. The barrier thickness, tins, is estimated to be 5 nm.

For our first device demonstration, we ud a metamorphic

InAlAs/InGaAs heterostructure grown on a GaAs substrate

with dual Si-doping layers which are located in the upper

InAlAs barrier to enhance electron tunneling at the contacts.

The channel is made out of In0.7Ga0.3As and is 10 nm thick.

IEDM10-69730.7.2R

[Ohm-μm]

2.5

1.0Lg = 50 nm

2.0

0.8VDS = 0.5 V

0.61.5

gm

0.41.0

ID0.20.5

0.0

0.0-0.4-0.20.00.20.40.6

-0.6VGS [V]

Fig. 6

Transfer and transconductance characteristics of 50 nm SAG

HEMT.

In order to understand the source resistance characteristics of

SAG HEMT fabricated by this process, we have directly

measured the effective source resistance, Rs*, by means of the

gate current injection technique [6], as shown in Fig. 8. The

source resistance Rs can be extracted by linear extrapolation of

RS* to zero Lg [7]. The extracted Rs is 147 Ohm-μm. This

value is around 30% lower than our previous report on lf-aligned W-bad devices [5].

Fig. 9 shows the maximum transconductance (gm) as a

function of Lg for our devices and state-of-the-art non-lf-aligned InAs PHEMTs [8] as well as earlier W-bad SAG

HEMTs [5] at VDS = 0.5 V. All the devices have about the

same tins = 5 nm. Our fabricated Mo-bad SAG devices show

improved transconductance and excellent scalability down to

Lg = 50 nm. In particularly, the Lg = 100 nm device exhibits a

gm of nearly 2 mS/μm at VDS = 0.5 V.

VDS = 0.5 V

1E-3

LG = 50 nmVDS = 0.05 V

1E-4

IDVDS = 0.5 V

1E-5

VDS = 0.05 V

1E-6IG

1E-7

-0.4-0.20.00.20.40.6

VGS [V]

Fig. 7 Subthreshold and IG characteristics of 50 nm Mo-bad SAG

HEMT.

0.30 W bad SAG HEMT : Waldron TED 2010 [5]

Mo bad SAG HEMT

0.28

0.26

0.24

0.22

Rs = 0.235

0.20

0.18

0.16Rs = 0.147

0.14

00240

LG [nm]

Fig. 8 Effective source resistance Rs* as a function of Lg

obtained from the gate current injection technique. The prent

devices are compared with tho from an earlier lf-aligned

technique [5]. The actual source resistance is the extrapolation

*

of Rs to Lg

= 0.

Microwave performance was characterized from 0.5 to 40

GHz. On-wafer open and short patterns were ud to subtract

pad capacitances and inductances from the measured device S-parameters. Fig. 10 plots H21, Unilateral gain (Ug), MSG and

K-factor for a Lg = 60 nm device at the peak gm bias condition

at VDS = 0.6 V (Lg = 60 nm is the smallest microwave device

available).

This work

2

InAs PHEMT [MIT IEDM 08]

tins = 5 nm

W-bad SAG HEMT [MIT IEDM 07]VDS = 0.5 V

14

LG [nm]

Fig. 9 Maximum transconductance (gm) as a function of gate length

for Mo-bad SAG HEMTs and state-of-the-art non-lf-aligned

InAs PHEMTs [8] as well as W-bad SAG HEMTs [5]. All

devices have tins=5 nm.

RS

[]*ID

[mA/μm]ID

&

IG

[A/μm]30.7.3gm

[mS/μm]gm [mS/μm]IEDM10-698 H214

Measured data Modeled data

VGS = 0.2 V, VDS =0.6 V

403

Ug

2

20

MAG/MSG

1

K

001101001,000

Frequency [GHz]

Fig. 10 Measured and modeled microwave characteristics of

Lg=60 nm Mo-bad SAG HEMT at VDS = 0.6 V.

Excellent values of fT = 580 GHz and fmax = 675 GHz have

been obtained. The measured characteristics are well described

by a simple lumped model constructed in ADS that predicts fT

= 600 GHz and fmax = 675 GHz. In addition, we measured this

device at the same bias point in a parate system up to 67 GHz.

We found fT = 590 GHz and fmax = 680 GHz giving credibility

to our measurements

Fig. 11 shows fT as a function of Lg for sub-100 nm InGaAs

and InAs HEMTs. The obtained fT value in our devices is the

highest ever reported in a HEMT above Lg = 50 nm and bodes

well for the future scalability of this device design. Fig. 12

shows favg = (fT x fmax)0.5 as a function of Lg for our SAG

HEMTs as well as reports from the literature. It is clear that our

new SAG technology attains record well-balanced high

frequency characteristics.

800

This work

800

600

400

NICT-Fujitsu200 NTT

Fraunhofer

NGC

MIT GIST

2

L [nm]

gFig. 12 favg = (fT x fmax)0.5 as a function of Lg for reported

InGaAs and InAs HEMTs in the literature, including Mo-bad

SAG HEMTs from this work.

Conclusions

H21,

MAG/MSG

and

Ug

[dB]We have demonstrated a new Mo-bad SAG HEMT

technology that delivers outstanding source resistance and

high frequency characteristics. In particular, Lg = 60 nm

devices exhibit gm = 2.1 mS/μm at VDS = 0.5 V, fT = 580 GHz

and fmax = 675 GHz at VDS = 0.6 V. Mo-bad SAG HEMTs

shows extremely low contact resistance of 7 ohm-μm and a

source resistance of 147 ohm-μm. This is the first

demonstration of a lf-aligned gate InGaAs HEMT

technology with state-of-the-art frequency respon. This

result strongly suggests a path towards obtaining Field-Effect

Transistors with fT and fmax both surpassing 1 THz.

References

[1] D.-H. Kim et al., IEDM, p. 719, 2008.

[2] K. Shinohara et al., IEEE EDL, p. 241, 2004.

[3] H. Matsuzaki et al.., IEDM, p. 775 , 2005.

[4] D. Morgan et al., IEEE TED, p. 2920, 2006.

[5] W. Niamh et al., IEEE TED, p. 297, 2010.

[6] D. R. Greenberg et al., IEEE TED, p. 1304, 1996.

[7] T.- W. Kim et al., IEDM, p. 483 , 2009.

[8] D.-H. Kim et al., IEEE EDL, p. 837, 2009.

Acknowledgements

This work was sponsored by Intel Corporation and FCRP-MSD at MIT. Device fabrication took place at the facilities of

the Microsystems Technology Laboratories (MTL), the

Scanning Electron Beam Lithography (SEBL) and the Nano-Structures Laboratory (NSL) at MIT. TEM analysis was

carried out at UNIST in Korea. Authors appreciate discussions

with Prof. Dimitir Antoniadis at work

400

NICT-Fujitsu

NTT200

Fraunhofer NGC

MIT

SNU others

4

Lg [nm]

Fig. 11 fT as a function of Lg for reported InGaAs and InAs

600IEDM10-699fT

[GHz]HEMTs in the literature, including Mo-bad SAG HEMTs in

this work.

30.7.4favg

=

(fT

x

fmax)0.5K

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